1. Field of the Invention
The present invention relates to a method and apparatus for image forming, and more particularly to a method and apparatus for image forming that is capable of effectively generating pixel clock pulses without using an extremely high frequency clock pulse.
2. Discussion of the Background
FIG. 1 illustrates a typical structure of a background electrophotographic image forming apparatus such as a digital copying apparatus. The background image forming apparatus of FIG. 1 includes a semiconductor laser unit 1, a polygon mirror 2, a scanning lens system 3, a photosensitive member 4, a photo-detector 5, an image process unit 6, a laser drive circuit 7, a clock pulse generator 8, and a phase sync circuit 9.
In the background image forming apparatus of FIG. 1, a laser light beam emitted from the laser unit 1 is reflected in a continuous and cyclic manner by the rotating polygon mirror 2 and becomes a scanning beam. Then, the scanning beam is directed to the surface of the photosensitive member 4 with the scanning lens system 3 to form a beam spot thereon. With this beam spot, an exposure process relative to the surface of the photosensitive member 4 is performed and therefore an electrostatic latent image is generated on the surface of the photosensitive member 4. In this process, the photo-detector 5 detects the scanning beam from line to line. The phase sync circuit 9 receives a clock pulse output from the clock pulse generator 8 and generates pixel clock pulses synchronized in phase from line to line with reference to the output from the photo-detector 5. The phase sync circuit 9 sends the thus-generated pixel clock pulses to the image process unit 6 and the laser drive circuit 7. In this way, the laser unit 1 controls a time period that the semiconductor laser emits laser light based on the image data generated by the image process unit 6 and the pixel clock pulses, synchronized in phase from line to line, and which is generated by the phase sync circuit 9. Thereby, the laser unit 1 can control an electrostatic latent image to be formed on the surface of the photosensitive member 4.
In the above-described optical scanning system, variations of distance between a deflective surface of a deflecting device such as a polygon mirror and a revolution shaft will cause the scanning beam to run on the surface of the photosensitive member at an undesired uneven scanning speed. Such an undesired uneven scanning speed will cause a jitter of an image and, as a result, an image quality is degraded. Therefore, correction for the scanning speed is needed to obtain a high image quality.
In a multiple beam optical system, a plurality of light sources may generate a plurality of laser beams with uneven oscillation wave lengths. In this case, an exposure displacement occurs particularly when the optical system does not correct a chromatic aberration of the scanning lens. Accordingly, when the beams spots generated by the laser light beams from the respective laser light sources run on the surface of the photosensitive member, the scanning widths will be different from each other. This also leads to a deterioration of an image quality and therefore the scanning widths are needed to be corrected.
For example, Japanese unexamined laid-open patent application publications, NO. 05-075199, No. 05-235446, No. 09-321376, No. 11-167081 and No. 2001-228415, describe background techniques for attempting to correct for the uneven scanning. These techniques basically are a frequency modulation method for changing a frequency of the pixel clock pulses to control a position of a light spot along the scanning line.
However, a circuit using such a frequency modulation method involves a complex control circuit for controlling pixel clock pulses and the complexness increases as the frequency modulation width becomes smaller. As a result, the circuit using the frequency modulation method cannot control the pixel clock pulses in a delicate manner.
This patent specification describes a novel pixel clock pulse generating apparatus for use in an image forming apparatus. In one example, this novel pixel clock pulse generating apparatus includes a high frequency clock pulse generator and a pixel clock pulse generator. The high frequency clock pulse generator generates relatively high frequency clock pulses. The pixel clock pulse generator receives phase data for instructing a transition time of pixel clock pulses and the relatively high frequency clock pulses generated by the high frequency clock pulse generator, and generates pixel clock pulses based on the phase data and the high frequency clock pulses.
This patent specification describes another novel pixel clock pulse generating apparatus for use in an image forming apparatus. In one example, this novel pixel clock pulse generating apparatus includes a high frequency clock pulse generator and a pixel clock pulse generator. The high frequency clock pulse generator generates relatively high frequency clock pulses. The pixel clock pulse generator receives phase data for instructing a transition time of pixel clock pulses and the relatively high frequency clock pulses generated by the high frequency clock pulse generator, and changes a frequency of pixel clock pulses based on the phase data and the high frequency clock pulses.
The transition time of pixel clock pulses may be synchronism with a transition time of the high frequency clock pulses.
In the above-mentioned pixel clock pulse generating apparatus, a frequency of the pixel clock pulses may be changed in steps of one clock cycle or a half clock cycle of the high frequency clock pulses.
This patent specification further describes another novel pixel clock pulse generating apparatus for use in an image forming apparatus. In one example, this novel pixel clock pulse generating apparatus includes a high frequency clock pulse generator, a counter, a comparator, and a controller. The high frequency clock pulse generator generates relatively high frequency clock pulses. The counter counts a number of the high frequency clock pulses generated by the high frequency clock pulse generator. The comparator compares the number of the high frequency clock pulses counted by the counter with phase data for instructing a transition time of pixel clock pulses. The controller performs a transition of a pixel clock pulse based on a result of comparison performed by the comparator.
The above-mentioned pixel clock pulse generating apparatus may further include a decoder for decoding the phase data and sending decoded data to the comparator.
The above-mentioned pixel clock pulse generating apparatus may further include a phase data memory for storing a plurality of phase data and sending the plurality of phase data in synchronism with the pixel clock pulses to the comparator.
The above-mentioned pixel clock pulse generating apparatus may further include a phase data memory and a decoder. The phase data memory stores a plurality of phase data and outputs the plurality of phase data in synchronism with the pixel clock pulses. The decoder receives the plurality of phase data output by the phase data memory, decodes the plurality of phase data, and sends the decoded phase data to the comparator.
The above-mentioned pixel clock pulse generating apparatus may further include a phase data memory and a synthesizer. The phase data memory stores a plurality of first phase data and outputs the plurality of phase data in synchronism with the pixel clock pulses. The synthesizer receives the plurality of first phase data output by the phase data memory and second phase data, synthesizes the plurality of first phase data and the second phase data, and sends synthesized phase data to the comparator.
The above-mentioned pixel clock pulse generating apparatus may further include a phase data memory, a synthesizer, and a decoder. The phase data memory stores a plurality of first phase data and outputs the plurality of phase data in synchronism with the pixel clock pulses. The synthesizer receives the plurality of first phase data output by the phase data memory and second phase data, synthesizes the plurality of first phase data and the second phase data, and outputs synthesized phase data. The decoder receives the synthesized phase data output from the synthesizer, decodes the synthesized phase data, and sends decoded phase data to the comparator.
The decoder may decode phase data having a bit width corresponding to an amount of phase shift into phase data having a bit width equal to a bit width used in a calculation.
The phase data memory may previously store a line of phase data and output the phase data line by line in synchronism with the pixel clock pulses.
The phase data memory may previously store a line of first phase data and output the phase data line by line in synchronism with the pixel clock pulses, and the synthesizer may synthesize the second phase data with the first phase data.
In the above-mentioned pixel clock pulse generating apparatus, a rising edge or a falling edge of each of the high frequency clock pulses may be detected and a number of the high frequency clock pulses is counted.
This patent specification further describes another novel pixel clock pulse generating apparatus for use in an image forming apparatus. In one example, this novel pixel clock pulse generating apparatus includes a high frequency clock pulse generator, a comparison value generator, first and second counters, first and second comparators, first and second clock pulse generators, and a clock pulse selector. The high frequency clock pulse generator generates relatively high frequency clock pulses. The comparison value generator generates a first comparison value and a second comparison value based on phase data indicating an amount of phase shift relative to pixel clock pulses and a status signal indicating a status of the pixel clock pulses. The first counter counts the high frequency clock pulses generated by the high frequency clock pulse generator by detecting a first varying point of each of the high frequency clock pulses. The first comparator compares an output value of the first counter with the first comparison value output from the comparison value generator. The first clock pulse generator generates a first clock pulse at the first varying point of the high frequency clock pulses based on a result of a comparison performed by the first comparator. The second counter counts the high frequency clock pulses generated by the high frequency clock pulse generator by detecting a second varying point of each of the high frequency clock pulses. The second comparator compares an output value of the second counter with the second comparison value output from the comparison value generator. The second clock pulse generator generates a second clock pulse at the second varying point of the high frequency clock pulses based on a result of a comparison performed by the second comparator. The pulse selector selects one of the first and second clock pulses and to output selected clock pulse as a pixel clock pulse.
The comparison value generator may generate a first value as the first comparison value and a second value as the second comparison value in accordance with the amount of phase shift indicated by the phase data when the status signal indicates that the pixel clock pulses are in a first status, and generate the second value as the first comparison value and the first value as the second comparison value in accordance with the amount of phase shift indicated by the phase data when the status signal indicates that the pixel clock pulses are in a second status.
The clock pulse selector may toggle between the first and second clock pulses in accordance with the phase data and the status of the pixel clock pulses indicated by the status signal.
This patent specification further describes a novel pixel clock pulse generating apparatus for use in an image forming apparatus. In one example, this novel pixel clock pulse generating apparatus includes a phase data memory which stores a plurality of phase data and sends the plurality of phase data in synchronism with the pixel clock pulses to the comparison value generator.
The above-mentioned novel pixel clock pulse generating apparatus may further include a phase data memory and a synthesizer. The phase data memory stores a plurality of first phase data and to send the plurality of first phase data in synchronism with the pixel clock pulses. The synthesizer receives the plurality of first phase data output by the phase data memory and second phase data, synthesizes the plurality of first phase data and the second phase data, and sends synthesized phase data to the comparison value generator.
The phase data memory may previously store a line of phase data and outputs the phase data line by line in synchronism with the pixel clock pulses.
The phase data memory may previously store a line of first phase data and outputs the phase data line by line in synchronism with the pixel clock pulses and the synthesizer synthesizes the second phase data with the first phase data.
The first varying point of each of the high frequency clock pulses may be a rising edge of each of the high frequency clock pulses and the second varying point of each of the high frequency clock pulses may be a falling edge of each of the high frequency clock pulses.
Further, this patent specification describes a novel method of generating pixel clock pulses. In one example, this novel method includes the steps of generating, instructing, and generating. The generating step generates relatively high frequency clock pulses. The instructing step instructs a transition time of pixel clock pulses with phase data. The generating step generates pixel clock pulses based on the phase data and the high frequency clock pulses.
This patent specification further describes another novel method of generating pixel clock pulse. In one example, this novel method includes the steps of generating, instructing, and changing. The generating step generates relatively high frequency clock pulses. The instructing step instructs a transition time of pixel clock pulses with phase data. The changing step changes a frequency of pixel clock pulses based on the phase data and the high frequency clock pulses.
Further, this patent specification describes a novel image forming apparatus. In one example, this novel image forming apparatus includes a photosensitive member, a pixel clock pulse generator, and a laser beam scanning mechanism. The pixel clock pulse generator includes a high frequency clock pulse generator and a pixel clock pulse generator. The high frequency clock pulse generator generates relatively high frequency clock pulses. The pixel clock pulse generator receives phase data for instructing a transition time of pixel clock pulses and the relatively high frequency clock pulses generated by the high frequency clock pulse generator and changes a frequency of pixel clock pulses based on the phase data and the high frequency clock pulses. The laser beam scanning mechanism generates a laser scanning beam based on the pixel clock pulses for cyclically scanning a surface of the photosensitive member to form an electrostatic latent image on the photosensitive member.
The laser beam scanning mechanism may generate a plurality of laser scanning beams based on the pixel clock pulses for cyclically scanning a surface of the photosensitive member with the plurality of laser scanning beams in a simultaneous manner to form an electrostatic latent image on the photosensitive member.
Further, this patent specification describes a novel method of image forming. In one example, this novel method includes the steps of generating, generating, instructing, changing, generating, and performing. The generating step generates relatively high frequency clock pulses. The generating step generates pixel clock pulses based on the relatively high frequency clock pulses. The instructing step instructs a transition time of the pixel clock pulses with phase data. The changing step changes a frequency of the pixel clock pulses based on the phase data and the high frequency clock pulses. The generating step generates a laser scanning beam based on the pixel clock pulses. The performing step performs a cyclic scanning with the laser scanning beam relative to a surface of a photosensitive member to form an electrostatic latent image on the photosensitive member.
The generating step may generate a plurality of laser scanning beams based on the pixel clock pulses and the performing step may perform the cyclic scanning with the plurality of laser scanning beams in a simultaneous manner relative to the surface of the photosensitive member to form an electrostatic latent image on the photosensitive member.
Further, this patent specification describes a novel image forming apparatus. In one example, a novel image forming apparatus include a photosensitive member, a pixel clock pulse generator, a laser light oscillator, an optical scanner, and a phase changer. The photosensitive member has a photosensitive surface. The pixel clock pulse generator is configured to generate pixel clock pulses. The laser light oscillator is configured to oscillate a plurality of laser light in accordance with the pixel clock pulses. The optical scanner is configured to convert the plurality of laser light into a plurality of scanning laser light beams that focus as a plurality of scanning laser light spots on the photosensitive surface of the photosensitive member and scan respective scanning lines starting from respective scanning start positions aligned in a sub-scanning direction on the photosensitive surface of the photosensitive member. The phase changer is configured to change a phase of the pixel clock pulses to control respective times when the plurality of laser light are oscillated by the laser light oscillator so as to correct deviations associated with the scanning laser light spots.
The laser light oscillator may include at least two laser light oscillating semiconductors or a laser light oscillating semiconductor that has a plurality of laser light emission points.
The deviations may occur in the scanning start positions in a main scanning direction and may be caused by differences in wave lengths of the respective of the plurality of laser light oscillated by the laser light oscillator.
The deviations may occur in the scanning start positions in a main scanning direction and may be caused due to manufacturing errors generated during a manufacturing of the laser light oscillator.
The optical scanner may include a laser light deflector configured to deflect the plurality of laser light. In this case, and the deviations may occur in the scanning start positions in a main scanning direction and may be caused due to a characteristic of the laser light deflector.
The deviations may occur in a scanning line length per unit time among the scanning laser light spots and the phase changer may change the phase of the pixel clock pulses to control respective times when the plurality of laser light are oscillated by the laser light oscillator so as to correct the deviations to be less than 1% relative to a predetermined scanning line length.
Further, this patent specification describes a novel image forming apparatus. In one example, a novel image forming apparatus includes a plurality of photosensitive members, a pixel clock pulse generator, a plurality of laser light oscillators, a plurality of optical scanners, and a phase changer. Each of the plurality of photosensitive members has a photosensitive surface. The pixel clock pulse generator is configured to generate pixel clock pulses. Each of the plurality of laser light oscillators includes at least one laser light oscillating semiconductor configured to oscillate laser light in accordance with the pixel clock pulses. The plurality of optical scanners are arranged to correspond to the plurality of laser light oscillators and to the plurality of photosensitive members on a one-to-one basis. Each of the plurality of optical scanners is configured to convert the laser light emitted by corresponding one of the plurality of laser light oscillator into a scanning laser light beam that focuses as a scanning laser light spot on the photosensitive surface of corresponding one of the plurality of the photosensitive members and scans a scanning line on the photosensitive surface of the corresponding one of the plurality of the photosensitive members. The phase changer is configured to change a phase of the pixel clock pulses to control respective times when the plurality of laser light are oscillated by the plurality of laser light oscillators so as to correct deviations in lengths of the scanning lines relative to a predetermined scanning time period among the plurality of photosensitive members.
The above-mentioned image forming apparatus may further includes a controller configured to control a driving of the laser light oscillator. This controller includes a high frequency clock pulse generator and an image data loader. The high frequency clock pulse generator is configured to generate a high frequency clock pulse. The image data loader is configured to load image data in synchronism with the high frequency clock pulse and the pixel clock pulse. In this configuration, the pixel clock pulse generator frequency-divides the high frequency clock pulse generated by the high frequency clock pulse generator to generate the pixel clock pulse and the phase changer shifts the phase of the pixel clock pulse to cause the image data loader to change a timing of loading the image data.
The high frequency clock pulse generator may include a phase synchronizer which includes a voltage control oscillator, a frequency divider, and a phase comparator. The voltage control oscillator is configured to oscillate laser light in accordance with a voltage applied. The frequency divider is configured to frequency-divide an output from the voltage control oscillator. The phase comparator is configured to compare a phase of an output from the frequency divider with a phase of a reference frequency and, based on a comparison result, to output a phase synchronous signal.
The pixel clock pulse generator may output the pixel clock pulse in synchronism with the phase synchronous signal output by the phase comparator.
The controller may include a pulse modulation pattern generator configured to generate a pulse modulation pattern relative to the laser light oscillated by the laser light oscillator in accordance with the output from the voltage control oscillator and the image data loaded by the image data loader.
The above-mentioned image forming apparatus may further include a pulse modulation controller configured to modulation-control the laser light oscillator in accordance with the pulse modulation pattern generated by the pulse modulation pattern generator to cause the laser light to be a frequency-modulated laser light. In this configuration, the phase changer may change the phase of the pixel clock pulses to control a time when the pulse modulation pattern generator generates the pulse modulation pattern.
The pixel clock pulse generator, the phase changer, the image data loader, the phase synchronizer, and the pulse modulation pattern generator may be integrated into a one-chip integrated circuit.
The pixel clock pulse generator, the phase changer, the controller, the phase synchronizer, and the pulse modulation pattern generator may be integrated into a one-chip integrated circuit.
This patent specification further describes a novel method of image forming. In one example, a novel method includes the steps of providing, generating, oscillating, converting, and changing. The providing step provides a photosensitive surface. The generating step generates pixel clock pulses. The oscillating step oscillates a plurality of laser light in accordance with the pixel clock pulses. The converting step converts the plurality of laser light into a plurality of scanning laser light beams that focus as a plurality of scanning laser light spots on the photosensitive surface and scan respective scanning lines starting from respective scanning start positions aligned in a sub-scanning direction on the photosensitive surface. The changing step changes a phase of the pixel clock pulses to control respective times when the plurality of laser light are oscillated by the oscillating step so as to correct deviations associated with the scanning laser light spots.
The oscillating step may use at least two laser light oscillating semiconductors or a laser light oscillating semiconductor that has a plurality of laser light emission points.
The deviations may occur in the scanning start positions in a main scanning direction and may be caused by differences in wave lengths of the respective of the plurality of laser light oscillated by the oscillating step.
The deviations may occur in the scanning start positions in a main scanning direction and may be caused due to manufacturing errors generated during a manufacturing of the laser light oscillating means.
The converting step may include a step of deflecting the plurality of laser light, and the deviations may occur in the scanning start positions in a main scanning direction and may be caused due to a characteristic of the deflecting step.
The deviations may occur in a scanning line length per unit time among the scanning laser light spots and the changing step may change the phase of the pixel clock pulses to control respective times when the plurality of laser light are oscillated by the oscillating step so as to correct the deviations to be less than 1% relative to a predetermined scanning line length.
The above-mentioned method may further include the step of controlling a driving of the laser light oscillator. This controlling step further include the steps of generating and loading. The generating step generates a high frequency clock pulse. The loading step loads image data in synchronism with the high frequency clock pulse and the pixel clock pulse. In this configuration, the pixel clock pulse generating step may frequency-divide the high frequency clock pulse generated by the high frequency clock pulse generating step to generate the pixel clock pulse and the changing step shifts the phase of the pixel clock pulse to cause the loading step to change a timing of loading the image data.
The high frequency clock pulse generating step may include the step of synchronizing which includes the steps of oscillating, frequency-dividing, and comparing. The oscillating step oscillates laser light in accordance with a voltage applied. The frequency-dividing step frequency-divides an output from the voltage control oscillating step. The comparing step compares a phase of an output from the frequency dividing step with a phase of a reference frequency and, based on a comparison result, to output a phase synchronous signal.
The pixel clock pulse generating step may output the pixel clock pulse in synchronism with the phase synchronous signal output by the comparing step.
The controlling step may further include the step of generating a pulse modulation pattern relative to the laser light oscillated by the laser light oscillating step in accordance with the output from the voltage control oscillating step and the image data loaded by the image data loading step.
The above-mentioned method may further include the steps of modulation-controlling the laser light oscillating step in accordance with the pulse modulation pattern generated by the pulse modulation pattern generating step to cause the laser light to be a frequency-modulated laser light. In this configuration, the phase changing step may change the phase of the pixel clock pulses to control a time when the pulse modulation pattern generating step generates the pulse modulation pattern.
The pixel clock pulse generating step, the phase changing step, the image data loading step, the phase synchronizing step, and the pulse modulation pattern generating step may be integrated into a one-chip integrated circuit.
The pixel clock pulse generating step, the phase changing step, the controlling step, the phase synchronizing step, and the pulse modulation pattern generating step may be integrated into a one-chip integrated circuit.